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US07689951B2 Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules 有权
设计规则检查系统和方法，用于检查集成电路设计符合多个设计规则

  • Patent Title: Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules
  • Patent Title (中): 设计规则检查系统和方法，用于检查集成电路设计符合多个设计规则
  • Application No.: US11574496
    Application Date: 2004-08-31
  • Publication No.: US07689951B2
    Publication Date: 2010-03-30
  • Inventor: Lionel Riviere Cazeaux
  • Applicant: Lionel Riviere Cazeaux
  • Applicant Address: US TX Austin
  • Assignee: Freescale Semiconductor, Inc.
  • Current Assignee: Freescale Semiconductor, Inc.
  • Current Assignee Address: US TX Austin
  • International Application: PCT/EP2004/011076 WO 20040831
  • International Announcement: WO2006/024324 WO 20060309
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules
Abstract:
In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.
Abstract(Chinese):

在用于检查集成电路设计是否符合规定各个几何参数的极限值的设计规则的设计规则检查系统中，使用非二进制函数来建模系统屈服损耗随着几何参数的值而变化的方式 。 这使得在几何参数符合设计规则但取值接近设计规则限制的情况下，可以将值分配给系统屈服损失。

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