Invention Grant
- Patent Title: Method of manufacturing a multilayer wiring board
- Patent Title (中): 多层布线板的制造方法
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Application No.: US11410984Application Date: 2006-04-26
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Publication No.: US07690109B2Publication Date: 2010-04-06
- Inventor: Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
- Applicant: Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
- Applicant Address: JP Tokyo
- Assignee: Dai Nippon Printing Co., Ltd.
- Current Assignee: Dai Nippon Printing Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2002-358844 20021211; JP2003-165066 20030610
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
Public/Granted literature
- US20060185141A1 Multilayer wiring board and manufacture method thereof Public/Granted day:2006-08-24
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