Invention Grant
- Patent Title: Method for evaluating impurity distribution under gate electrode without damaging silicon substrate
- Patent Title (中): 评估栅极电极杂质分布而不损坏硅衬底的方法
-
Application No.: US11407918Application Date: 2006-04-21
-
Publication No.: US07691649B2Publication Date: 2010-04-06
- Inventor: Kazuo Hashimi , Hidekazu Sato
- Applicant: Kazuo Hashimi , Hidekazu Sato
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2005-365074 20051219
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L29/94

Abstract:
A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.
Public/Granted literature
Information query
IPC分类: