Invention Grant
US07691681B2 Chip scale package having flip chip interconnect on die paddle 有权
芯片级封装,在芯片上具有倒装芯片互连

  • Patent Title: Chip scale package having flip chip interconnect on die paddle
  • Patent Title (中): 芯片级封装,在芯片上具有倒装芯片互连
  • Application No.: US12191542
    Application Date: 2008-08-14
  • Publication No.: US07691681B2
    Publication Date: 2010-04-06
  • Inventor: Cheonhee Lee
  • Applicant: Cheonhee Lee
  • Applicant Address: US CA Fremont
  • Assignee: ChipPAC, Inc.
  • Current Assignee: ChipPAC, Inc.
  • Current Assignee Address: US CA Fremont
  • Agent Robert D. Atkins
  • Main IPC: H01L21/00
  • IPC: H01L21/00
Chip scale package having flip chip interconnect on die paddle
Abstract:
A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
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