Invention Grant
- Patent Title: Chip scale package having flip chip interconnect on die paddle
- Patent Title (中): 芯片级封装,在芯片上具有倒装芯片互连
-
Application No.: US12191542Application Date: 2008-08-14
-
Publication No.: US07691681B2Publication Date: 2010-04-06
- Inventor: Cheonhee Lee
- Applicant: Cheonhee Lee
- Applicant Address: US CA Fremont
- Assignee: ChipPAC, Inc.
- Current Assignee: ChipPAC, Inc.
- Current Assignee Address: US CA Fremont
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
Public/Granted literature
- US20080299705A1 Chip Scale Package Having Flip Chip Interconnect on Die Paddle Public/Granted day:2008-12-04
Information query
IPC分类: