Invention Grant
US07691693B2 Method for suppressing layout sensitivity of threshold voltage in a transistor array
有权
抑制晶体管阵列中阈值电压的布局灵敏度的方法
- Patent Title: Method for suppressing layout sensitivity of threshold voltage in a transistor array
- Patent Title (中): 抑制晶体管阵列中阈值电压的布局灵敏度的方法
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Application No.: US11757294Application Date: 2007-06-01
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Publication No.: US07691693B2Publication Date: 2010-04-06
- Inventor: Victor Moroz , Dipankar Pramanik
- Applicant: Victor Moroz , Dipankar Pramanik
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Warren S. Wolfeld
- Main IPC: H01L21/338
- IPC: H01L21/338
Abstract:
A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout.
Public/Granted literature
- US20080296698A1 METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY Public/Granted day:2008-12-04
Information query
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