Invention Grant
US07691713B2 Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film
失效
制造半导体器件的方法，该半导体器件能够抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低
- Patent Title: Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film
- Patent Title (中): 制造半导体器件的方法，该半导体器件能够抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低
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Application No.: US11767734Application Date: 2007-06-25
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Publication No.: US07691713B2Publication Date: 2010-04-06
- Inventor: Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
- Applicant: Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2003-143438 20030521
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
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