Invention Grant
- Patent Title: Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
- Patent Title (中): 具有位于由源/漏区产生的边界内的位错环的半导体器件及其制造方法
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Application No.: US11042415Application Date: 2005-01-25
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Publication No.: US07691714B2Publication Date: 2010-04-06
- Inventor: Antonio Luis Pacheco Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
- Applicant: Antonio Luis Pacheco Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/337
Abstract:
The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
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