Invention Grant
US07691716B2 Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
有权
具有绝大多数载流子积累层的垂直双极晶体管作为用于SOI BiCMOS的子集电极,具有降低的掩埋氧化物厚度以用于低衬底偏置操作
- Patent Title: Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
- Patent Title (中): 具有绝大多数载流子积累层的垂直双极晶体管作为用于SOI BiCMOS的子集电极,具有降低的掩埋氧化物厚度以用于低衬底偏置操作
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Application No.: US12144998Application Date: 2008-06-24
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Publication No.: US07691716B2Publication Date: 2010-04-06
- Inventor: Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
- Applicant: Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L21/8222

Abstract:
The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.
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