Invention Grant
US07691718B2 Dual layer hard mask for block salicide poly resistor (BSR) patterning
失效
双层硬掩模用于块状硅化物电阻(BSR)图案化
- Patent Title: Dual layer hard mask for block salicide poly resistor (BSR) patterning
- Patent Title (中): 双层硬掩模用于块状硅化物电阻(BSR)图案化
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Application No.: US12005944Application Date: 2007-12-27
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Publication No.: US07691718B2Publication Date: 2010-04-06
- Inventor: Joodong Park , Chia-Hong Jan , Paul Reese
- Applicant: Joodong Park , Chia-Hong Jan , Paul Reese
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Ryder, Lu, Mazzeo and Konieczny, LLC
- Agent Douglas J. Ryder
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
Public/Granted literature
- US20090170273A1 Dual layer hard mask for block salicide poly resistor (BSR) patterning Public/Granted day:2009-07-02
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