Method of forming bit line in semiconductor device

Invention Grant

US07691741B2 Method of forming bit line in semiconductor device 失效

Title translation: 在半导体器件中形成位线的方法

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Patent Title: Method of forming bit line in semiconductor device
Patent Title (中): 在半导体器件中形成位线的方法
Application No.: US11401585

Application Date: 2006-04-11
Publication No.: US07691741B2

Publication Date: 2010-04-06
Inventor: Sung Hoon Lee
Applicant: Sung Hoon Lee
Applicant Address: KR Icheon-si
Assignee: Hynix Semiconductor Inc.
Current Assignee: Hynix Semiconductor Inc.
Current Assignee Address: KR Icheon-si
Agency: Marshall, Gerstein & Borun LLP
Priority: KR10-2005-0033712 20050422
Main IPC: H01L21/4763
IPC: H01L21/4763

Method of forming bit line in semiconductor device

Abstract:

A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch thickness of a photo mask. The remaining trench oxide film is etched using the hard mask nitride film as a mask, thus forming a trench. The etch-stop nitride film and the hard mask nitride film are etched on condition that an oxide film has a high selectivity with respect to a nitride film. Accordingly, the loss of a top surface of the trench oxide film can be minimized and a bit line can be formed to have a uniform height. In accordance with the invention, bit line resistance and capacitance variation can be reduced and the reliability of a device can be improved.

Abstract(Chinese):

一种形成半导体器件的位线的方法，其中在半导体衬底上形成蚀刻停止氮化物膜，沟槽氧化物膜和硬掩模氮化物膜。将硬掩模氮化物膜和沟槽氧化物膜蚀刻到光掩模的有限蚀刻厚度。使用硬掩模氮化物膜作为掩模蚀刻剩余的沟槽氧化膜，从而形成沟槽。在氧化膜相对于氮化物膜具有高选择性的条件下蚀刻蚀刻停止氮化物膜和硬掩模氮化物膜。因此，可以使沟槽氧化膜的上表面的损失最小化，并且可以形成具有均匀高度的位线。根据本发明，可以降低位线电阻和电容变化，并且可以提高器件的可靠性。

Public/Granted literature

US20060240673A1 Method of forming bit line in semiconductor device Public/Granted day:2006-10-26

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）