Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Invention Grant

US07691747B2 Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures 有权

Title translation: 用于通过硅通孔形成无源电路元件到背面互连结构的半导体器件和方法

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Patent Title: Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
Patent Title (中): 用于通过硅通孔形成无源电路元件到背面互连结构的半导体器件和方法
Application No.: US11947617

Application Date: 2007-11-29
Publication No.: US07691747B2

Publication Date: 2010-04-06
Inventor: Yaojian Lin , Haijing Cao , Qing Zhang Zhang , Kang Chen , Jianmin Fang
Applicant: Yaojian Lin , Haijing Cao , Qing Zhang Zhang , Kang Chen , Jianmin Fang
Applicant Address: SG Singapore
Assignee: STATS ChipPAC, Ltd
Current Assignee: STATS ChipPAC, Ltd
Current Assignee Address: SG Singapore
Agent Robert D. Atkins
Main IPC: H01L21/44
IPC: H01L21/44

Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Abstract:

A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract(Chinese):

半导体晶片包含其上形成有多个有源器件的衬底。在基板上形成模拟电路。模拟电路可以是电感，金属 - 绝缘体 - 金属电容或电阻。电感由铜制成。在衬底中形成贯穿衬底通孔（TSV）。导电材料沉积在与模拟电路电接触的TSV中。在与TSV电接触的衬底的背面上形成凸起下金属化层。焊料材料沉积在UBM层上。焊料材料被回流以形成焊料凸块。在基板的顶表面上形成引线接合。在TSV和UBM之间形成再分配层。模拟电路通过TSV电连接到衬底背面的焊料凸块。

Public/Granted literature

US20090140381A1 Semiconductor Device and Method for Forming Passive Circuit Elements with Through Silicon Vias to Backside Interconnect Structures Public/Granted day:2009-06-04

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/44	....用H01L21/36至H01L21/428各组不包含的方法或设备在半导体材料上制造电极的