Invention Grant
- Patent Title: Matched analog CMOS transistors with extension wells
- Patent Title (中): 具有扩展阱的匹配模拟CMOS晶体管
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Application No.: US11948172Application Date: 2007-11-30
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Publication No.: US07692217B2Publication Date: 2010-04-06
- Inventor: Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
- Applicant: Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L27/148
- IPC: H01L27/148

Abstract:
One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
Public/Granted literature
- US20090140346A1 MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS Public/Granted day:2009-06-04
Information query
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