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US07692319B2 Efficient provision of alignment marks on semiconductor wafer 失效
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Efficient provision of alignment marks on semiconductor wafer
Abstract:
A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.
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