Invention Grant
- Patent Title: Level conversion circuit with low consumption current characteristics
- Patent Title (中): 电平转换电路具有低功耗电流特性
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Application No.: US12181729Application Date: 2008-07-29
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Publication No.: US07692470B2Publication Date: 2010-04-06
- Inventor: Shinji Yamamoto , Toshihiko Takeda , Taketo Kunihisa
- Applicant: Shinji Yamamoto , Toshihiko Takeda , Taketo Kunihisa
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-197555 20070730
- Main IPC: H03L5/00
- IPC: H03L5/00

Abstract:
A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.
Public/Granted literature
- US20090033402A1 LEVEL CONVERSION CIRCUIT Public/Granted day:2009-02-05
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