A switched-capacitor circuit performing two-phase operation with a sampling phase and an amplification phase comprising: an inverter having a common source type input transistor and a load transistor; a first capacitor whose first terminal is connected to a gate of the input transistor serving as an input of the inverter; a first switch which connects between the input (the gate of the input transistor) and the output of the inverter, which turns on during the sampling phase and turns off during the amplification phase; a second switch which connects a second terminal of the first capacitor to an input voltage terminal during the sampling phase, and connects the second terminal of the first capacitor to the output terminal of the inverter during the amplification phase; a second capacitor whose first terminal is connected to a gate of the load transistor of the inverter and whose second terminal is connected to the second terminal of the first capacitor; and a third switch which connects the first terminal of the second capacitor to a bias voltage terminal during the sampling phase, and turns off the first terminal of the second capacitor from the bias voltage during the amplification phase.