Invention Grant
- Patent Title: Apparatus and method for preventing snap back in integrated circuits
- Patent Title (中): 集成电路中防止闪回的装置和方法
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Application No.: US11870322Application Date: 2007-10-10
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Publication No.: US07692483B2Publication Date: 2010-04-06
- Inventor: Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
- Applicant: Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
- Applicant Address: US CA San Jose
- Assignee: Atmel Corporation
- Current Assignee: Atmel Corporation
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H03H3/356
- IPC: H03H3/356

Abstract:
A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.
Public/Granted literature
- US20090096501A1 APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS Public/Granted day:2009-04-16
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