Invention Grant
US07692483B2 Apparatus and method for preventing snap back in integrated circuits 有权
集成电路中防止闪回的装置和方法

Apparatus and method for preventing snap back in integrated circuits
Abstract:
A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.
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