Invention Grant
US07692943B2 Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
失效
半导体存储器件布局包括用于向N个井和P井提供井电压的高杂质阱抽头区域
- Patent Title: Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
- Patent Title (中): 半导体存储器件布局包括用于向N个井和P井提供井电压的高杂质阱抽头区域
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Application No.: US12000135Application Date: 2007-12-10
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Publication No.: US07692943B2Publication Date: 2010-04-06
- Inventor: Kenichi Osada , Takayuki Kawahara , Ken Yamaguchi , Yoshikazu Saito , Naoki Kitai
- Applicant: Kenichi Osada , Takayuki Kawahara , Ken Yamaguchi , Yoshikazu Saito , Naoki Kitai
- Applicant Address: JP Tokyo JP Tokyo
- Assignee: Renesas Technology Corp.,Hitachi Ulsi Systems Co., Ltd.
- Current Assignee: Renesas Technology Corp.,Hitachi Ulsi Systems Co., Ltd.
- Current Assignee Address: JP Tokyo JP Tokyo
- Agency: Stites & Harbison PLLC
- Agent Juan Carlos A. Marquez, Esq.
- Priority: JP2002-378947 20021227
- Main IPC: G11C5/02
- IPC: G11C5/02
Abstract:
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
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