Invention Grant
US07692969B2 Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell
有权
非易失性半导体存储器件包括多个存储器单元和耦合到存储器单元的端部的虚拟单元
- Patent Title: Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell
- Patent Title (中): 非易失性半导体存储器件包括多个存储器单元和耦合到存储器单元的端部的虚拟单元
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Application No.: US12408785Application Date: 2009-03-23
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Publication No.: US07692969B2Publication Date: 2010-04-06
- Inventor: Hiroaki Hazama , Norio Ohtani
- Applicant: Hiroaki Hazama , Norio Ohtani
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2002-286055 20020930
- Main IPC: G11C16/06
- IPC: G11C16/06
Abstract:
A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cell.
Public/Granted literature
- US20090185414A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2009-07-23
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