Invention Grant
- Patent Title: Testing methods of a semiconductor integrated incorporating a high-frequency receiving circuit and a demodulation circuit
- Patent Title (中): 包含高频接收电路和解调电路的集成电路的测试方法
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Application No.: US11600143Application Date: 2006-11-16
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Publication No.: US07693223B2Publication Date: 2010-04-06
- Inventor: Shinya Kishigami
- Applicant: Shinya Kishigami
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JP2005-334972 20051118
- Main IPC: H04L27/00
- IPC: H04L27/00

Abstract:
A semiconductor integrated circuit that can be tested in a reduced test time includes a high-frequency receiving circuit for receiving a high-frequency signal, and a demodulation circuit for demodulating a signal received from the high-frequency receiving circuit. The demodulation circuit includes a Static Random Access Memory (SRAM), an SRAM control circuit, and a test data transmitting circuit. The SRAM control circuit receives, from a semiconductor test device, test data for driving and testing the high-frequency receiving circuit, and writes the test data into the SRAM. The test data transmitting circuit reads out from the SRAM test data for driving and testing the high-frequency receiving circuit, and transmits the test data to the high-frequency receiving circuit.
Public/Granted literature
- US20070115735A1 Semiconductor integrated circuits and test methods thereof Public/Granted day:2007-05-24
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