A system, apparatus, method and article to encode, clock recover, and sample data bits are described. The apparatus may include a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input. The first clock input to receive an encoded signal from a single-wire. The encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit. The pulsed digital module to capture an edge of the encoded signal at the first clock input in accordance with a logic level coupled to the first data input. A delay module comprising a delay input is coupled to the data output and a delay output is coupled to the reset input. The delay module to delay the captured edge by a predetermined period and to generate a delay signal from the delay output after the predetermined period. The pulsed digital module is to generate a first clock edge of the sampling clock at the data output after the predetermined period. An apparatus, system, and method to embed a sampling clock signal via an encoded signal comprising n bits and to transmit the encoded signal to a single-wire as a serial bit sequence of n bits. The encoded signal represents a logic bit having an encoding clock period TCLK. Other embodiments are described and claimed.