A memory controller utilizing a performance monitor to modulate the level of data security applied to the data being transferred to and from memory depending on the performance. The performance monitor tracks the response time for access to the memory over a defined time window. The response times are then compared to a predefined allowable response time. This comparison is done over a predefined window of time. When the actual response times exceed the allowable limits, the level of encryption is limited until performance parameters fall within the limits selected. The frequency with which the encryption mechanism is adjusted may also be predefined. Data transfers continue as the controller monitors system performance and controls the level of security applied to the data according to that performance data. The performance modulation can be different depending on what unit is accessing memory in multi-unit systems.