Invention Grant
US07694176B2 Fault-tolerant computer and method of controlling same 失效
容错计算机及其控制方法

  • Patent Title: Fault-tolerant computer and method of controlling same
  • Patent Title (中): 容错计算机及其控制方法
  • Application No.: US11305122
    Application Date: 2005-12-19
  • Publication No.: US07694176B2
    Publication Date: 2010-04-06
  • Inventor: Ryuta Niino
  • Applicant: Ryuta Niino
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Agency: Young & Thompson
  • Priority: JP2004-369388 20041221
  • Main IPC: G06F11/00
  • IPC: G06F11/00
Fault-tolerant computer and method of controlling same
Abstract:
A fault-tolerant computer has duplex systems each comprising a CPU subsystem for controlling access to a CPU and a storage unit, and an IO subsystem for controlling data which are input to the IO subsystem from an external circuit and output from the IO subsystem to the external circuit. Data with a transmission time assigned thereto is transmitted from one of the IO subsystems to the other IO subsystem, and is received asynchronously by the other IO subsystem. The other IO subsystem records a reception time of the data, and calculates an ideal reception time using the transmission time assigned to the data. A clock shift in the other IO subsystem with respect to the one IO subsystem is calculated from the calculated ideal reception time and the recorded reception time. Thereafter, the counter in the other IO subsystem is changed based on the calculated clock shift, and data is received using the changed counter.
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