Invention Grant
- Patent Title: Debugging system and method
- Patent Title (中): 调试系统和方法
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Application No.: US11520806Application Date: 2006-09-14
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Publication No.: US07694182B2Publication Date: 2010-04-06
- Inventor: Shigeya Takagi , Yasuhiko Hamada , Hidetaka Matsumoto
- Applicant: Shigeya Takagi , Yasuhiko Hamada , Hidetaka Matsumoto
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-267335 20050914
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
In a multitask execution environment, a debugging device performs debugging setting for rewriting part of original recording content in a memory area shared by at least two tasks, and debugging cancellation for restoring rewritten recording content back to original recording content. The debugging device stores a memory area used by each task, and address information specifying each debugging target task and a respective address. When task switching occurs, if a next task is not a debugging target, recording content at a physical address specified by address information other than that of the next task and within the physical address space range used by the next task is put into a post-debugging cancellation state. If the next task is a debugging target task, in addition to the above processing, recording content at the physical address specified by the address information of the next task is put into a post-debugging setting state.
Public/Granted literature
- US20070061627A1 Debugging system and method Public/Granted day:2007-03-15
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