Invention Grant
US07694197B2 Integrated circuit comprising a test mode secured by detection of the state of a control signal
有权
集成电路包括通过检测控制信号的状态而保证的测试模式
- Patent Title: Integrated circuit comprising a test mode secured by detection of the state of a control signal
- Patent Title (中): 集成电路包括通过检测控制信号的状态而保证的测试模式
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Application No.: US11484359Application Date: 2006-07-10
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Publication No.: US07694197B2Publication Date: 2010-04-06
- Inventor: Frédéric Bancel , David Hely
- Applicant: Frédéric Bancel , David Hely
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics, SA
- Current Assignee: STMicroelectronics, SA
- Current Assignee Address: FR Montrouge
- Agency: Graybeal Jackson LLP
- Agent Lisa K. Jorgenson; Kevin D. Jablonski
- Priority: FR0507281 20050708; FR0507282 20050708
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/30

Abstract:
An electronic circuit comprises configurable cells driven by command signals to adopt either a standard mode of operation in which they are integrated into a logic circuit, or a test mode in which they provide information on this logic circuit. The circuit includes a spy circuit capable of detecting an abnormal excitation of certain of the conductors through which the command signals travel, thus preventing fraudulent extraction of data out of the configurable cells. The spy circuit includes a logic combination circuit and a state detection cell.
Public/Granted literature
- US20070033463A1 Integrated circuit comprising a test mode secured by detection of the state of a control signal Public/Granted day:2007-02-08
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