Invention Grant
- Patent Title: Integrated circuit having built-in self-test features
- Patent Title (中): 集成电路具有内置的自检功能
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Application No.: US11779354Application Date: 2007-07-18
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Publication No.: US07694200B2Publication Date: 2010-04-06
- Inventor: Glenn A. Forrest , Washington Lamar
- Applicant: Glenn A. Forrest , Washington Lamar
- Applicant Address: US MA Worcester
- Assignee: Allegro Microsystems, Inc.
- Current Assignee: Allegro Microsystems, Inc.
- Current Assignee Address: US MA Worcester
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00

Abstract:
An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and distribute a built-in self-test signal. The built-in self-test signal can emulate signals internal to the integrated circuit during normal operation, and/or the built-in self-test signal can have other signal characteristics representative of signals other than those signals internal to the integrated circuit during normal operation.
Public/Granted literature
- US20090024889A1 INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES Public/Granted day:2009-01-22
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