Invention Grant
US07694205B2 Method and apparatus for providing a read channel having combined parity and non-parity post processing
有权
用于提供具有组合奇偶校验和非奇偶校验后处理的读通道的方法和装置
- Patent Title: Method and apparatus for providing a read channel having combined parity and non-parity post processing
- Patent Title (中): 用于提供具有组合奇偶校验和非奇偶校验后处理的读通道的方法和装置
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Application No.: US11067851Application Date: 2005-02-28
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Publication No.: US07694205B2Publication Date: 2010-04-06
- Inventor: Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
- Applicant: Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
- Applicant Address: NL Amsterdam
- Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee Address: NL Amsterdam
- Agency: Merchant & Gould
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H03M13/00
Abstract:
A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.
Public/Granted literature
- US20060195775A1 Method and apparatus for providing a read channel having combined parity and non-parity post processing Public/Granted day:2006-08-31
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