Invention Grant
US07694248B2 Method and apparatus for supporting verification, and computer product
失效
支持验证的方法和装置,以及计算机产品
- Patent Title: Method and apparatus for supporting verification, and computer product
- Patent Title (中): 支持验证的方法和装置,以及计算机产品
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Application No.: US11249361Application Date: 2005-10-14
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Publication No.: US07694248B2Publication Date: 2010-04-06
- Inventor: Toshihito Shimizu , Koichi Itaya , Hitoshi Watanabe
- Applicant: Toshihito Shimizu , Koichi Itaya , Hitoshi Watanabe
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Yokohama
- Priority: JP2005-080752 20050318
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation of the target circuit; a diversion determining unit that determines, based on a result of analysis by the analyzing unit, whether the description data is divertible to the test mode operation; and a generating unit that generates setting data for the test mode operation based on a result of determination by the determining unit.
Public/Granted literature
- US20060209603A1 Method and apparatus for supporting verification, and computer product Public/Granted day:2006-09-21
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