Invention Grant
US07694251B2 Method and system for verifying power specifications of a low power design
有权
用于验证低功率设计功率规格的方法和系统
- Patent Title: Method and system for verifying power specifications of a low power design
- Patent Title (中): 用于验证低功率设计功率规格的方法和系统
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Application No.: US11590076Application Date: 2006-10-30
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Publication No.: US07694251B2Publication Date: 2010-04-06
- Inventor: Bharat Chandramouli , Huan-Chih Tsai , Manish Pandey , Chih-Chang Lin , Madan M. Das
- Applicant: Bharat Chandramouli , Huan-Chih Tsai , Manish Pandey , Chih-Chang Lin , Madan M. Das
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agent Stephen C. Durant
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.
Public/Granted literature
- US20080127015A1 Method and system for verifying power specifications of a low power design Public/Granted day:2008-05-29
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