Invention Grant
- Patent Title: Method and system for static verification of multi-voltage circuit design
- Patent Title (中): 多电压电路设计静态验证方法与系统
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Application No.: US11738483Application Date: 2007-04-21
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Publication No.: US07694252B1Publication Date: 2010-04-06
- Inventor: Saptarshi Biswas , Srikanth Jadcherla , Sriram Kotni , Debabrata Bagchi
- Applicant: Saptarshi Biswas , Srikanth Jadcherla , Sriram Kotni , Debabrata Bagchi
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan & Fleming LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Verification of a design for a multi-voltage circuit which defines a plurality of iso-voltage rail blocks, and which comprises voltage state information for the iso-voltage-rail blocks. Verification includes generating cross-over information regarding a cross-over signal between two iso-voltage-rail blocks, identifying the voltage state relationship between the two iso-voltage-rail blocks based on the voltage state information, and verifying the validity of the cross-over signal based on the determined voltage state relationship.
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