An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as seen from the direction normal to the plane. The lowermost vias are disposed so as to fit in a 4-row, 1-column rectangle, and the uppermost vias are disposed so as to fit in a 2-row, 2-column rectangle. The center of a via unit, which comprises the uppermost vias, as seen from the direction normal to the plane is disposed at the intersecting portion of the lowermost wiring layer and uppermost wiring layer. The center of a via unit, which comprises the lower vias, as seen from the direction normal to the plane is offset by a prescribed amount from the center of the via unit, which comprises the uppermost vias, as seen from the direction normal to the plane.