Invention Grant
- Patent Title: Method of identifying specific holes in an interface guiding plate
- Patent Title (中): 识别接口导板中特定孔的方法
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Application No.: US11732087Application Date: 2007-04-02
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Publication No.: US07695766B2Publication Date: 2010-04-13
- Inventor: Neil Adams , Stuart Eickhoff , Jon Hample
- Applicant: Neil Adams , Stuart Eickhoff , Jon Hample
- Applicant Address: US MN Maple Grove
- Assignee: Circuit Check
- Current Assignee: Circuit Check
- Current Assignee Address: US MN Maple Grove
- Agency: Altera Law Group, LLC
- Main IPC: B05D3/00
- IPC: B05D3/00

Abstract:
A circuit board tester that uses a dual-stage translation to bring a unit under test (UUT) into physical and electric contact first with a series of tall probes, then with a series of short probes. Initially, the UUT is mounted on a support plate, and spaced apart from both the tall and short probes. First, in order to perform a functional test on the UUT, a first vacuum stage is engaged, and atmospheric pressure translates the UUT longitudinally until contact is made with a first hard stop, defining a first position. At this first position, the UUT is in contact with a series of tall probes, and is spaced apart from a series of short probes. After a function test is performed, a second vacuum stage is engaged in addition to, and independent of, the first vacuum stage. Atmospheric pressure translates the UUT longitudinally until contact is made with a second hard stop, defining a second position.
Public/Granted literature
- US20080231299A1 Vacuum chamber with two-stage longitudinal translation for circuit board testing Public/Granted day:2008-09-25
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