Invention Grant
- Patent Title: Wafer-level chip packaging process and chip package structure
- Patent Title (中): 晶圆级芯片封装工艺和芯片封装结构
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Application No.: US11616901Application Date: 2006-12-28
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Publication No.: US07696008B2Publication Date: 2010-04-13
- Inventor: Chien-Yu Chen
- Applicant: Chien-Yu Chen
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Jiang Chyun IP Office
- Priority: TW95100424A 20060105
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/40
Abstract:
A wafer-level chip packaging process includes the following steps. First, a wafer having a plurality of chip units, an active surface, and a corresponding back surface is provided. Each chip unit has a plurality of pads on the active surface. Next, a plurality of through holes is formed under the pads. The through holes are filled with a conductive material such that the conductive material within each through hole is electrically connected to corresponding one of the pads and a portion of the conductive material is exposed and protrudes from the back surface of the wafer. Thereafter, a transparent adhesive layer is formed on the active surface. Next, a transparent cover panel is disposed on the transparent adhesive layer such that the transparent cover panel is connected to the wafer through the transparent adhesive layer. Afterwards, a singulation step is performed to form a plurality of independent chip package structures.
Public/Granted literature
- US20070158673A1 WAFER-LEVEL CHIP PACKAGING PROCESS AND CHIP PACKAGE STRUCTURE Public/Granted day:2007-07-12
Information query
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