Invention Grant
US07696051B2 Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate
失效
制造在凹陷衬底上具有掺杂的外延生长源/漏区的MOSFET的方法
- Patent Title: Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate
- Patent Title (中): 制造在凹陷衬底上具有掺杂的外延生长源/漏区的MOSFET的方法
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Application No.: US11177185Application Date: 2005-07-07
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Publication No.: US07696051B2Publication Date: 2010-04-13
- Inventor: You-seung Jin , Jong-hyon Ahn
- Applicant: You-seung Jin , Jong-hyon Ahn
- Applicant Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR2003-00838 20030107
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.
Public/Granted literature
- US20050282344A1 MOSFET and method of fabricating the same Public/Granted day:2005-12-22
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