Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns

Invention Grant

US07696081B2 Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns 失效

Title translation: 制造半导体器件的方法，其使用普通光掩模和相移掩模来定义互连图案

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Patent Title: Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns
Patent Title (中): 制造半导体器件的方法，其使用普通光掩模和相移掩模来定义互连图案
Application No.: US12010793

Application Date: 2008-01-30
Publication No.: US07696081B2

Publication Date: 2010-04-13
Inventor: Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
Applicant: Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
Applicant Address: JP Tokyo
Assignee: Renesas Technology Corp.
Current Assignee: Renesas Technology Corp.
Current Assignee Address: JP Tokyo
Agency: McDermott Will & Emery LLP
Priority: JP2007-021732 20070131
Main IPC: H01L21/475
IPC: H01L21/475

Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns

Abstract:

According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps.A step of preparing a phase shift mask and a normal photomask.A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring.A step of stacking an interlayer insulating film on the second wiring layer.A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask.A step of burying a metal in the first opening and the second opening.A step of providing a pad to be overlaid on the first and second openings.

Abstract(Chinese):

根据本发明的一个实施例，制造半导体器件的方法包括以下步骤。制备相移掩模和普通光掩模的步骤。在半导体衬底上堆叠第一布线层，并且在第一布线层上进一步层叠第二布线层的步骤。第二布线层包括第二布线和第三布线。在第二布线层上堆叠层间绝缘膜的步骤。在层间绝缘膜中形成第二布线露出的第一开口和通过光刻法使用普通光掩模使第三布线曝光的第二开口的步骤。在第一开口和第二开口中埋入金属的步骤。提供覆盖在第一和第二开口上的垫的步骤。

Public/Granted literature

US20080217786A1 Semiconductor device and method of manufacturing semiconductor device Public/Granted day:2008-09-11

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/469	......在半导体材料上形成绝缘层的，例如，用于掩膜的或应用光刻技术的（密封层入H01L21/56）以及这些层的后处理
H01L21/475	.......应用掩膜的