Invention Grant
- Patent Title: Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
- Patent Title (中): 使用三元铜合金获得低电阻和大晶粒尺寸互连的方法
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Application No.: US09994395Application Date: 2001-11-26
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Publication No.: US07696092B2Publication Date: 2010-04-13
- Inventor: Sergey D. Lopatin , Paul R. Besser , Pin-Chin Connie Wang
- Applicant: Sergey D. Lopatin , Paul R. Besser , Pin-Chin Connie Wang
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong, Mori & Steiner, P.C.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/48
Abstract:
A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.
Public/Granted literature
- US20040005773A1 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect Public/Granted day:2004-01-08
Information query
IPC分类:
