Invention Grant
- Patent Title: Solid-state imaging device having wiring layer which includes lamination of silicide layer in order to reduce wiring resistance, and manufacturing method for the same
- Patent Title (中): 具有包括硅化物层的叠层以便降低布线电阻的布线层的固态成像装置及其制造方法
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Application No.: US12015930Application Date: 2008-01-17
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Publication No.: US07696546B2Publication Date: 2010-04-13
- Inventor: Tatsuya Hirata , Shouzi Tanaka , Ryohei Miyagawa
- Applicant: Tatsuya Hirata , Shouzi Tanaka , Ryohei Miyagawa
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-010457 20070119; JP2007-261208 20071004
- Main IPC: H01L31/062
- IPC: H01L31/062

Abstract:
A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.
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Information query
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