Invention Grant
- Patent Title: Selective CESL structure for CMOS application
- Patent Title (中): CMOS应用的选择性CESL结构
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Application No.: US11349804Application Date: 2006-02-08
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Publication No.: US07696578B2Publication Date: 2010-04-13
- Inventor: Chia-Lin Chen , Min-jan Chen , Jau-Jey Wang
- Applicant: Chia-Lin Chen , Min-jan Chen , Jau-Jey Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L27/092
- IPC: H01L27/092

Abstract:
A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.
Public/Granted literature
- US20070181951A1 Selective CESL structure for CMOS application Public/Granted day:2007-08-09
Information query
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