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US07696578B2 Selective CESL structure for CMOS application 有权
CMOS应用的选择性CESL结构

Selective CESL structure for CMOS application
Abstract:
A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.
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