Invention Grant
US07696801B2 Reset method for clock triggering digital circuit and related signal generating apparatus utilizing the reset method
有权
使用复位方法的时钟触发数字电路和相关信号发生装置的复位方法
- Patent Title: Reset method for clock triggering digital circuit and related signal generating apparatus utilizing the reset method
- Patent Title (中): 使用复位方法的时钟触发数字电路和相关信号发生装置的复位方法
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Application No.: US11755001Application Date: 2007-05-30
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Publication No.: US07696801B2Publication Date: 2010-04-13
- Inventor: Sung-Hung Yeh , Kuo-Uei Yang
- Applicant: Sung-Hung Yeh , Kuo-Uei Yang
- Applicant Address: TW Hsinchu
- Assignee: Realtek Semiconductor Corp.
- Current Assignee: Realtek Semiconductor Corp.
- Current Assignee Address: TW Hsinchu
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Priority: TW95121577A 20060616
- Main IPC: H03K3/02
- IPC: H03K3/02
Abstract:
The present invention discloses a reset method for a digital circuit. The method includes: providing a clock signal to the digital circuit; keeping the clock signal at a logic level according to a first indicating signal; generating a reset signal for resetting the digital circuit; and recovering the clock signal to the digital circuit according to a second indicating signal.
Public/Granted literature
- US20070290732A1 RESET METHOD FOR DIGITAL CIRCUIT AND RELATED SIGNAL GENERATING APPARATUS Public/Granted day:2007-12-20
Information query
IPC分类:
