Invention Grant
US07696917B2 Encode circuit and analog-digital converter comprising a digital average unit and a logical boundary detection unit
失效
编码电路和模数转换器,包括数字平均单元和逻辑边界检测单元
- Patent Title: Encode circuit and analog-digital converter comprising a digital average unit and a logical boundary detection unit
- Patent Title (中): 编码电路和模数转换器,包括数字平均单元和逻辑边界检测单元
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Application No.: US11798098Application Date: 2007-05-10
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Publication No.: US07696917B2Publication Date: 2010-04-13
- Inventor: Kouji Matsuura , Koichi Ono , Kiyoshi Makigawa
- Applicant: Kouji Matsuura , Koichi Ono , Kiyoshi Makigawa
- Applicant Address: JP
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP
- Agency: Rader Fishman & Grauer PLLC
- Agent Ronald P. Kananen
- Priority: JP2006-132550 20060511
- Main IPC: H03M1/36
- IPC: H03M1/36

Abstract:
An encode circuit includes a digital average unit that receives cyclic thermometer codes or standard thermometer codes, and that reduces a bubble error in the received thermometer codes by a majority vote rule, a logical boundary detection unit that detects a logical boundary in the thermometer codes output from the digital average unit, and an encoder unit that generates output codes based on output signals from the logical boundary detection unit.
Public/Granted literature
- US20070262887A1 Encode circuit and analog-digital converter Public/Granted day:2007-11-15
Information query
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