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Invention Grant
US07697249B2 Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages 有权
使用具有相同的MOS晶体管和半导体芯片的钳位电路以及钳位电压的方法

Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages
Abstract:
A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
Abstract(Chinese):

提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。 当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。 钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。

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