Invention Grant
- Patent Title: Memory system and semiconductor integrated circuit
- Patent Title (中): 存储系统和半导体集成电路
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Application No.: US12209661Application Date: 2008-09-12
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Publication No.: US07697315B2Publication Date: 2010-04-13
- Inventor: Shunichi Iwanari
- Applicant: Shunichi Iwanari
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2001-252523 20010823
- Main IPC: G11C11/22
- IPC: G11C11/22

Abstract:
A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved.
Public/Granted literature
- US20090016093A1 MEMORY SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2009-01-15
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