Invention Grant
- Patent Title: Logic design modeling and interconnection
- Patent Title (中): 逻辑设计建模与互连
-
Application No.: US10824489Application Date: 2004-04-15
-
Publication No.: US07698118B2Publication Date: 2010-04-13
- Inventor: Frederic Reblewski
- Applicant: Frederic Reblewski
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Banner & Witcoff, Ltd.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K17/693 ; H03K19/00 ; H03K19/173 ; H03K19/177

Abstract:
A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.
Public/Granted literature
- US20050234692A1 Logic design modeling and interconnection Public/Granted day:2005-10-20
Information query