Invention Grant
US07698482B2 Multiple data rates in integrated circuit device serial interface
有权
集成电路设备串行接口中的多种数据速率
- Patent Title: Multiple data rates in integrated circuit device serial interface
- Patent Title (中): 集成电路设备串行接口中的多种数据速率
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Application No.: US11177007Application Date: 2005-07-08
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Publication No.: US07698482B2Publication Date: 2010-04-13
- Inventor: Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
- Applicant: Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ropes & Gray LLP
- Agent Jeffrey H. Ingerman
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F5/00

Abstract:
A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
Public/Granted literature
- US20070011370A1 Multiple data rates in programmable logic device serial interface Public/Granted day:2007-01-11
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