Invention Grant
US07698535B2 Asynchronous multiple-order issue system architecture 失效
异步多阶问题系统架构

Asynchronous multiple-order issue system architecture
Abstract:
An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
Public/Granted literature
Information query
Patent Agency Ranking
0/0