Invention Grant
US07698666B2 Method and system for model-based design and layout of an integrated circuit
有权
集成电路基于模型设计和布局的方法和系统
- Patent Title: Method and system for model-based design and layout of an integrated circuit
- Patent Title (中): 集成电路基于模型设计和布局的方法和系统
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Application No.: US11648150Application Date: 2006-12-29
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Publication No.: US07698666B2Publication Date: 2010-04-13
- Inventor: Eric Nequist , Richard Brashears
- Applicant: Eric Nequist , Richard Brashears
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.
Public/Granted literature
- US20080163134A1 Method and system for model-based design and layout of an integrated circuit Public/Granted day:2008-07-03
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