Invention Grant
US07702983B2 Scan compression architecture for a design for testability compiler used in system-on-chip software design tools
有权
扫描压缩架构，用于系统级芯片软件设计工具中用于可测试性编译器的设计
- Patent Title: Scan compression architecture for a design for testability compiler used in system-on-chip software design tools
- Patent Title (中): 扫描压缩架构，用于系统级芯片软件设计工具中用于可测试性编译器的设计
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Application No.: US11744631Application Date: 2007-05-04
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Publication No.: US07702983B2Publication Date: 2010-04-20
- Inventor: Marco Casarsa
- Applicant: Marco Casarsa
- Applicant Address: IT Agrate Brianza (MI)
- Assignee: STMicroelectronics S.R.L.
- Current Assignee: STMicroelectronics S.R.L.
- Current Assignee Address: IT Agrate Brianza (MI)
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Agent Lisa K. Jorgenson
- Priority: EP06009228 20060504
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
A scan compression architecture for a design for a testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor configuration connected to a first predetermined set of pins, and a second scan architecture including a second scan compressor/decompressor configuration connected to a subset of the pins. The first scan architecture is selectively enabled for executing a scan test with a low time. The second scan architecture is for executing a scan test with high parallelism.
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