Invention Grant
- Patent Title: Semiconductor device having diffusion layers as bit lines and method for manufacturing the same
- Patent Title (中): 具有作为位线的扩散层的半导体器件及其制造方法
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Application No.: US12337023Application Date: 2008-12-17
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Publication No.: US07704803B2Publication Date: 2010-04-27
- Inventor: Nobuyoshi Takahashi , Fumihiko Noro , Kenji Sato
- Applicant: Nobuyoshi Takahashi , Fumihiko Noro , Kenji Sato
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-124657 20050422
- Main IPC: H01L21/8246
- IPC: H01L21/8246

Abstract:
A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.
Public/Granted literature
- US20090104765A1 SEMICONDUCTOR DEVICE HAVING DIFFUSION LAYERS AS BIT LINES AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2009-04-23
Information query
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