Invention Grant
- Patent Title: Buried stress isolation for high-performance CMOS technology
- Patent Title (中): 埋地应力隔离用于高性能CMOS技术
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Application No.: US12099195Application Date: 2008-04-08
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Publication No.: US07704839B2Publication Date: 2010-04-27
- Inventor: MeiKei Ieong , Zhibin Ren , Haizhou Yin
- Applicant: MeiKei Ieong , Zhibin Ren , Haizhou Yin
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.
Public/Granted literature
- US20080185658A1 Buried Stress Isolation for High-Performance CMOS Technology Public/Granted day:2008-08-07
Information query
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