Invention Grant
- Patent Title: Method of manufacturing semiconductor device and control system
- Patent Title (中): 制造半导体器件和控制系统的方法
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Application No.: US12073235Application Date: 2008-03-03
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Publication No.: US07704877B2Publication Date: 2010-04-27
- Inventor: Hidetaka Nambu
- Applicant: Hidetaka Nambu
- Applicant Address: JP Kawasaki, Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kawasaki, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-068584 20070316
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the anti-reflective film is etched through the upper resist film used as a mask, wherein the anti-reflective film is etched while varying a value of at least one etching condition correlative to Δ(L2−L1), expressing dimensional shift of width L2 of opening of the recess formed in the insulating film, with respect to width L1 of opening of the upper resist film, so as to reduce the dimensional shift Δ(L2−L1) as the aperture ratio of the opening to be formed in the upper resist film increases, depending on the aperture ratio.
Public/Granted literature
- US20080227224A1 Method of manufacturing semiconductor device and control system Public/Granted day:2008-09-18
Information query
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