Invention Grant
US07704892B2 Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current
有权
具有局部互连层和用于防止电流泄漏的蚀刻停止图案的半导体器件
- Patent Title: Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current
- Patent Title (中): 具有局部互连层和用于防止电流泄漏的蚀刻停止图案的半导体器件
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Application No.: US11517087Application Date: 2006-09-07
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Publication No.: US07704892B2Publication Date: 2010-04-27
- Inventor: Dong-kyun Nam , Heon-jong Shin , Hyung-tae Ji
- Applicant: Dong-kyun Nam , Heon-jong Shin , Hyung-tae Ji
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Mills & Onello, LLP
- Priority: KR01-55064 20010907
- Main IPC: H01L21/22
- IPC: H01L21/22 ; H01L23/528

Abstract:
A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.
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